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Fortaegis Technologies is seeking a Design Verification Engineer to verify RTL designs for FPGA and ASIC products. Lees de informatie in deze vacature zorgvuldig door om precies te begrijpen wat er van potentiële kandidaten wordt verwacht.
Job Description 5+ years of experience in RTL functional verification for FPGA and/or ASIC designs Advanced knowledge of SystemVerilog and UVM Hands-on experience with verification EDA tools (e.g., Siemens, Cadence, Synopsys) Strong analytical and problem-solving abilities with
